), V. D. Kunz, P. Ashburn, D. Donaghy*, and S. Hall*MOSFET's are being continuously scaled down in channel length due to the increasing need for higher packing density and higher device speed. Vertical MOSFET's would avoid the limitations of optical lithography , because the channel length is defined by layer thickness or etching. Furthermore vertical MOSFET's have almost naturally a double gate structure which can reduce short channel effects. Recently vertical n-MOSFET's have been fabricated by ion implantation and other processes qualified for production [1]. Main disadvantage of the vertical MOSFET is the large overlap capacitance of the gate with source and drain.
We have fabricated vertical p-MOSFET's by ion implantation, and we will present data of this batch, which includes logic gates and oscillators. Different issues related to the pillar structure, such as the effect of corners will be discussed. To reduce the parasitic gate capacitance in vertical MOSFET's a simple self-aligned process has been developed using nitride fillets on the sidewalls of the trench or pillar followed by a local oxidation. This will result in an oxide layer on all exposed planar surfaces, but no oxide layer on the protected vertical channel area [2]. Simulations and TEM micrographs will support the measured reduction in parasitic capacitance.
