Integrated Circuit (IC) scaling, as envisioned by Moore, has become the productivity criterion by which the IC industry has grown at approximately 25-30% compound annual growth rate (CAGR) (i.e., increased number of transistors, decreased cost per transistor, etc.) Although Moore’s law will eventually saturate, it has been the cornerstone by which the IC industry gauges its growth as, for example, in the International Technology Roadmap for Semiconductors (ITRS). We will examine the device structures envisioned to sustain Moore’s law for the next 15 years, during which the current MOSFET physical gate length of about 65 nm is expected to be scaled to about 9 nm. In the later regime of transistors with very short physical gate length, conventional planar, bulk CMOS devices may be replaced by non-planar device configurations utilizing, in some combination, elevated source / drains, high-k gate dielectric materials, metal gate electrodes and SOI technologies. We will also briefly discuss several device initiatives beyond CMOS technologies, including alternative non-silicon materials, and the extreme challenges (both business and technical) such an approach entails.