), A. Agarwal, C. Lim, A. Hou, A. Jain,
P. J. Chen, P. Lysaght, J. Barnett, D. Riley, Y. Kim,
G. Bersuker, P. Zeitzoff, G.A. Brown, C. Young, J. Gutt, N. Chaudhary,
J. Tamim, M. I. Gardner, and R. W. MurtoThe pervasiveness of the microelectronics revolution has continued for the past 40 years, with IC density quadrupling every three to four years in conjunction with improved transistor performance (i.e., speed). Device scaling has been the engine driving this revolution. NMOS transistor gate delay (CV/I) less than 1 psec has been achieved for physical gate lengths (Lphys) as small as 15-20 nm with a planar CMOS oxynitride gate dielectric structure (approximately 0.8 nm physical thickness, VDD = 0.85-0.75 V) with comparable PMOS behavior [1,2]. It has been anticipated that in this physical gate length regime a higher-k gate dielectric with equivalent oxide thickness (EOT) approximately 0.5-0.8 nm will be required for high-performance applications, based on the 2001 edition of the International Technology Roadmap for Semiconductors (ITRS) [3] The initial utilization of the higher-k gate dielectric, however, is anticipated in about 2005 for low-standby power applications, with Lphys about 45 nm, an EOT of about 1.8 nm and a gate leakage current anticipated to be approximately 1 pA/_ m [3]. A number of investigators have examined the influence of high-k gate dielectrics [4,5], the selection of dual metal gate electrodes with differing work functions for CMOS optimization [6], elevated source drain [7], fully depleted SOI [7] as well as other considerations for future CMOS configurations. We shall summarize several challenges and opportunities for ensuring compatibility of integrated high-k gate stack systems in current planar CMOS processes. These issues include chemical etching of the high-k gate dielectric [8], issues associated with the plasma etching of the gate stack system _ selectivity, plasma damage, compatibility with spacer and spacer sidewall profile, screen dielectric for source/drain implantation and chemical etching of the high-k gate dielectric material [9], high-k contamination control in the fab line [8,10] and assessment of the thermal stability of the high-k gate dielectric with subsequent thermal processes, including source drain [5,11,12]. Finally, brief comments will be made about the importance of the role of diagnostic techniques [13] as well as the host of reliability considerations.
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